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The figure below shows the pin configuration of the MTi 1-series module. Pins 18, 19 and 20 are only used on the MTi-7/8. For MTi-1/2/3 these pins need not be connected (DNC).
Pin configuration of the MTi 1-series module (top view)
The MTi 1-series modules are designed to be used as peripheral devices in embedded systems. The MTi 1-series modules support inter-integrated circuit (I2C), serial peripheral interface (SPI) and universal asynchronous receiver/transmitter (UART) protocols for the communication between the MTi 1-series module and host CPU. The I2C and SPI protocols are well suited for communication between integrated circuits and on-board peripherals. To select the correct communication interface, PSEL1 and PSEL0 should be configured accordingly (see #PSEL serial host communication interface selection). For interface specifications, see the table below.
|
Interface |
|
Min |
Typ |
Max |
Units |
|---|---|---|---|---|---|
|
I2C |
Host I2C Interface Speed |
|
|
400 |
kHz |
|
SPI |
Host SPI Interface Speed |
|
|
2 |
MHz |
|
Clock Duty Cycle |
30 |
50 |
70 |
% |
|
|
UART |
Baud Rates |
|
921.6 |
4000 |
kbps |
The MTi 1-series modules have four modes of peripheral interfacing. Only one mode can be used at a time and this is determined by the state of peripheral selection pins PSEL0 and PSEL1 at start up. The table below specifies how the PSEL lines select the peripheral interface. Note that the module has internal pull‑ups (30 kΩ – 50 kΩ). Not connecting PSEL results in a value of 1, connecting PSEL to GND results in a value of 0.
|
Interface |
PSEL1 |
PSEL0 |
|---|---|---|
|
I2C |
1 |
1 |
|
SPI |
1 |
0 |
|
UART half-duplex |
0 |
1 |
|
UART full-duplex |
0 |
0 |
I2C is the default interface (when PSEL1 and PSEL0 pins are floating or connected to VDDIO). The I2C SCL and SDA pins are open drain and therefore they need pull-up resistors to VDDIO (R2 and R3 in the figure below; typical value: 2.7 kΩ).
External components (I2C interface)
The MTi 1-series module acts as an I2C Slave. The I2C slave address is determined by the ADD0, ADD1 and ADD2 pins. These pins are pulled-up internally, so when left unconnected, the address selection defaults to ADD[0..2] = 111. The table below shows a list of all possible I2C addresses.
|
I2C address |
ADD2 |
ADD1 |
ADD0 |
|---|---|---|---|
|
0x1D |
0 |
0 |
0 |
|
0x1E |
0 |
0 |
1 |
|
0x28 |
0 |
1 |
0 |
|
0x29 |
0 |
1 |
1 |
|
0x68 |
1 |
0 |
0 |
|
0x69 |
1 |
0 |
1 |
|
0x6A |
1 |
1 |
0 |
|
0x6B (default) |
1 |
1 |
1 |
For the SPI interface, PSEL1 can be left floating or pulled-up to VDDIO and the PSEL0 pin needs to be connected to GND, as shown below.
Connections (SPI interface)
For the UART full-duplex interface, the PSEL1 and PSEL0 pins need to be connected to GND, as shown below. The UART full-duplex communications mode can be used without hardware flow control. In this case, the CTS line needs to be tied low (GND) to make the MTi 1-series transmit. For the UART half‑duplex interface, PSEL1 needs to be connected to GND and the PSEL0 pin must be left floating (see table above).
Connections (UART interface full-duplex)
The MTi-7/8 variants of the MTi 1- series module family support external inputs from a GNSS receiver like the u-blox MAX-M8. For the GNSS receiver, the UART communication and PPS/TIMEPULSE pins of the receiver need to be connected to the AUX_TX, AUX_RX and SYNC_PPS pins of the MTi-7/8 module. See figure below for schematic details and table below for interface specifications.
GNSS receiver interface specifications
|
Interface |
|
Typ |
Max |
Units |
|---|---|---|---|---|
|
UART |
Baud Rates |
115.2 |
2000 |
kbps |
Besides the GNSS receiver, the MTi-7/8 also supports an external barometer. The following barometers are supported:
For the barometer, the SPI pins need to be connected to the AUX_nCS, AUX_MOSI, AUX_MISO and AUX_SCK pins of the MTi-7/8 module. See the figure below for schematic details.
Connections (GNSS interface)
The I/O interface specifications are listed in the table below:
|
I/O interface |
Symbol |
Min |
Max |
Unit |
Description |
|---|---|---|---|---|---|
|
SYNC_IN |
VIL |
|
0.3 · VDDIO |
V |
Input low voltage |
|
VIH |
0.45 · VDDIO + 0.3 |
|
V |
Input high voltage |
|
|
VHYS |
0.45 · VDDIO + 0.3 |
|
V |
Threshold hysteresis voltage |
|
|
nRST* |
VIL |
|
0.3 · VDDIO |
V |
Only drive momentarily |
|
RPU |
30 |
50 |
kΩ |
Pull-up resistor |
|
|
TP |
20 |
|
µs |
Generated reset pulse duration |
The reset pin is active low. Drive this pin with an open drain output or momentary (tactile) switch to GND. During normal operation, this pin should be left floating, as this line is also used for internal resets. This pin has an internal weak pull-up to VDDIO.
The SYNC_IN pin accepts an external trigger, on which the MTi 1-series sends out the latest available data message. The SYNC_IN pin is 5V tolerant and can be connected directly to an external device. Please make sure that the MTi 1-series and the external device are connected to or have the same common GND. The table I/O Pins shows the electrical specifications.
These pins are reserved for future use.